1. Field of the Invention
This invention relates to a phase comparing circuit and a PLL (phase locked loop) circuit.
2. Description of the Prior Art
Some electronic apparatuses such as VTR's (video tape recorders), disk players, and communication equipments include a device for generating a clock signal from a reproduced or received information signal. The generated clock signal is used for timing control related to the detection of data in the information signal. It is well-known to use a PLL (phase locked loop) circuit in such a clock-signal generating device.
A reproducing side of a PCM-VTR conforming to Partial Response Class 4 includes a waveform equalizer which removes inter-symbol interference components from a reproduced information signal. The waveform equalizer processes the reproduced information signal into a 3-level information signal substantially free from inter-symbol interference. The waveform equalizer is followed by a partial response detector and a clock-signal generating circuit which are parallel to each other. The partial response detector converts the 3-level information signal into a bi-level information signal (a binary information signal or a digital information signal). The clock-signal generating circuit recovers or generates a clock signal from the 3-level information signal. A D-flip-flop following the partial response detector and the clock-signal generating circuit samples and holds the bi-level information signal at a timing determined by the generated clock signal. The sapling and holding process results in the extraction or recovery of original data (information) from the bi-level information signal.
In the reproducing side of the above-indicated PCM-VTR, there are two different signal transmission paths between the waveform equalizer and the D-flip-flop. One of the signal transmission paths includes the partial response detector, while the other signal transmission path includes the clock-signal generating circuit. Since the signal transmission paths differ from each other, there is a difference between the phases of signals appearing at the output ends of the signal transmission paths. To compensate for such a phase difference, a signal delay device is interposed in one of the signal transmission paths.
During a playback process, a variation in the reproducing speed causes a change in the data rate (the data transmission rate) related to the reproduced information signal. In the reproducing side of the above-indicated PCM-VTR, it tends to be difficult to maintain suitable compensation for the phase difference when the data rate related to the reproduced information signal changes.